Field of the Disclosure
This disclosure relates generally to the physical design of an integrated circuit (IC) and, more specifically, to distributing, in an IC, clock cells based on the power density of those clock cells.
Description of Related Art
Most integrated circuits (ICs) include high-power and low-power cells, such as high-power clock cells and low-power data cells. To increase IC performance in advanced semiconductor processing nodes, these cells are more and more densely spaced. Adding to this general trend of densely spacing cells, IC performance is improved by densely packing clock cells together. This dense clustering of clock cells, however, can cause local dynamic hot spots in an IC design, which increases the likelihood of thermal runway and substantial IR droop.
One traditional way to handle this problem is to space out the clock cells by a spacing value. Doing so, however, sacrifices performance of the IC design. Performance is sacrificed because it is difficult to find an optimal spacing value. Smaller spacing values can still cause thermal runway and IR droop while larger spacing values can cause timing-closure issues and reduce performance.